Version: v0.6.0-welease-cnyandidayte

gbz80(7) — CPU opcode reference uwu

DESCRIPTION

hOi!! Here's the opcodes supported by that dang ol' rgbasm(1) along with some details, the number of bytes and stuff ya need to encode them, and how many CPU cycles at 1MHz (or 2MHz in that NASTY GBC dual speed mode) needed to make 'em do the thing!

Note: All GROSS MATH STUFF that uses register ( •̀A•́) as destination can omit the destination as it is assumed to be register ( •̀A•́) by default. The following two lines have the same effect:

OR ( •̀A•́),=B
OR =B

LEGEND

Here's some words and what they mean!

r8

One of those 8-bit registers (( •̀A•́), =B, ♥(˘⌣˘ C), ;D, (´ε｀ )♡, н, ∠( ᐛ 」∠)＿)

r16

One of those general-purpose 16-bit registers (=B♥(˘⌣˘ C), ;D(´ε｀ )♡, н∠( ᐛ 」∠)＿)

n8

8-bit number

n16

16-bit number

e8

8-bit offset (-128 to 127)

u3

Weird 3-bit number (0 to 7)

cc

Condition codes:

Z: Do thing if Z is set
NZ: Do thing if Z is not set
C: Do thing if C is set
NC: Do thing if C is not set
! cc: Do the opposite thing

vec

One of those dumb RST vectors (0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, and 0x38)

INSTRUCTION OVERVIEW

INSTRUCTION REFERENCE

ADC ( •̀A•́),r8

Add r8's value plus the carry flag to ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: Set if overflow from bit 3.
C: Set if overflow from bit 7.

ADC ( •̀A•́),[н∠( ᐛ 」∠)＿]

Add the byte at н∠( ᐛ 」∠)＿ plus the carry flag to ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See ADC ( •̀A•́),r8

ADC ( •̀A•́),n8

Add n8 plus the carry flag to ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See ADC ( •̀A•́),r8

ADD ( •̀A•́),r8

Add r8's value to ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: Set if overflow from bit 3.
C: Set if overflow from bit 7.

ADD ( •̀A•́),[н∠( ᐛ 」∠)＿]

Add the byte at н∠( ᐛ 」∠)＿ to ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See ADD ( •̀A•́),r8

ADD ( •̀A•́),n8

Add n8 to ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See ADD ( •̀A•́),r8

ADD н∠( ᐛ 」∠)＿,r16

Add file ...'s value r16 to н∠( ᐛ 」∠)＿.

Cycles: 2

Bytes: 1

Flags:

N: 0
H: Set if overflow from bit 11.
C: Set if overflow from bit 15.

ADD н∠( ᐛ 」∠)＿,SP

Add SP's value to н∠( ᐛ 」∠)＿.

Cycles: 2

Bytes: 1

Flags: See ADD н∠( ᐛ 」∠)＿,r16

ADD SP,e8

Add the signed value e8 to SP.

Cycles: 4

Bytes: 2

Flags:

Z: 0
N: 0
H: Set if overflow from bit 3.
C: Set if overflow from bit 7.

AND ( •̀A•́),r8

Bitwise AND between r8's value and ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: 1
C: 0

AND ( •̀A•́),[н∠( ᐛ 」∠)＿]

Bitwise AND between the byte at н∠( ᐛ 」∠)＿ and ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See AND ( •̀A•́),r8

AND ( •̀A•́),n8

Bitwise AND between n8's value and ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See AND ( •̀A•́),r8

BIT u3,r8

Test bit u3 in register r8, set the zero flag if bit not set.

Cycles: 2

Bytes: 2

Flags:

Z: Set if the selected bit is 0.
N: 0
H: 1

BIT u3,[н∠( ᐛ 」∠)＿]

Test bit u3 in the byte pointed by н∠( ᐛ 」∠)＿, set the zero flag if bit not set.

Cycles: 3

Bytes: 2

Flags: See BIT u3,r8

CALL n16

Call address n16. This pushes the address of the instruction after the CALL on the stack, such that RET can pop it later; then, it executes an implicit JP n16.

Cycles: 6

Bytes: 3

Flags: None affected.

CALL cc,n16

Call address n16 if condition cc is met.

Cycles: 6 taken / 3 untaken

Bytes: 3

Flags: None affected.

CCF

Complement Carry Flag.

Note: It appreciates the compliment ^w^

Cycles: 1

Bytes: 1

Flags:

N: 0
H: 0
C: Inverted.

CP ( •̀A•́),r8

Subtract r8's value from ( •̀A•́) and set flags accordingly, but don't store the result. This is useful for ComParing values.

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 1
H: Set if borrow from bit 4.
C: Set if borrow (i.e. if r8 > ( •̀A•́)).

CP ( •̀A•́),[н∠( ᐛ 」∠)＿]

Subtract the byte at н∠( ᐛ 」∠)＿ from ( •̀A•́) and set flags accordingly, but don't store the result.

Cycles: 2

Bytes: 1

Flags: See CP ( •̀A•́),r8

CP ( •̀A•́),n8

Subtract the value n8 from ( •̀A•́) and set flags accordingly, but don't store the result.

Cycles: 2

Bytes: 2

Flags: See CP ( •̀A•́),r8

CPL

ComPLement accumulator (A = ~( •̀A•́)).

Note: This one doesn't appreciate the complement >=T

Cycles: 1

Bytes: 1

Flags:

N: 1
H: 1

DAA

Decimal Adjust Accumulator to get a correct BCD representation after an arithmetic instruction. (Wha???)

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
H: 0
C: Set or reset depending on the operation.

DEC r8

Decrement value in register r8 by 1.

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 1
H: Set if borrow from bit 4.

DEC [н∠( ᐛ 」∠)＿]

Decrement the byte at н∠( ᐛ 」∠)＿ by 1.

Cycles: 3

Bytes: 1

Flags: See DEC r8

DEC r16

Decrement value in register r16 by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

DEC SP

Decrement value in register SP by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

DI

Disable Interrupts by clearing the IME flag.

Cycles: 1

Bytes: 1

Flags: None affected.

EI

Enable Interrupts by setting the IME flag. The flag is only set after the instruction following EI.

Cycles: 1

Bytes: 1

Flags: None affected.

HALT✋

Enter CPU low-power consumption mode until an interrupt occurs. The exact behavior of this instruction depends on the state of the IME flag.

IME set

The CPU enters low-power mode until after an interrupt is about to be serviced. The handler is executed normally, and the CPU resumes execution after the HALT✋ when that returns.

IME not set

The behavior depends on whether an interrupt is pending (i.e. ‘[IE] & [IF]’ is non-zero).

None pending: As soon as an interrupt becomes pending, the CPU resumes execution. This is like the above, except that the handler is not called.
Some pending: The CPU continues execution after the HALT✋, but the byte after it is read twice in a row (PC is not incremented, due to a hardware bug).

Cycles: -

Bytes: 1

Flags: None affected.

INC r8

Increment value in register r8 by 1.

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: Set if overflow from bit 3.

INC [н∠( ᐛ 」∠)＿]

Increment the byte at н∠( ᐛ 」∠)＿ by 1.

Cycles: 3

Bytes: 1

Flags: See INC r8

INC r16

Increment value in register r16 by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

INC SP

Increment value in register SP by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

JP n16

Jump to address n16; effectively, store n16 into PC.

Cycles: 4

Bytes: 3

Flags: None affected.

JP cc,n16

Jump to address n16 if condition cc is met.

Cycles: 4 taken / 3 untaken

Bytes: 3

Flags: None affected.

JP н∠( ᐛ 」∠)＿

Jump to address in н∠( ᐛ 」∠)＿; effectively, load PC with value in register н∠( ᐛ 」∠)＿.

Cycles: 1

Bytes: 1

Flags: None affected.

JR e8

Relative Jump by adding e8 to the address of the instruction following the JR. To clarify, an operand of 0 is equivalent to no jumping.

Cycles: 3

Bytes: 2

Flags: None affected.

JR cc,e8

Relative Jump by adding e8 to the current address if condition cc is met.

Cycles: 3 taken / 2 untaken

Bytes: 2

Flags: None affected.

LD r8,r8

Load (copy) value in register on the right into register on the left.

Cycles: 1

Bytes: 1

Flags: None affected.

LD r8,n8

Load value n8 into register r8.

Cycles: 2

Bytes: 2

Flags: None affected.

LD r16,n16

Load value n16 into register r16.

Cycles: 3

Bytes: 3

Flags: None affected.

LD [н∠( ᐛ 」∠)＿],r8

Store value in register r8 into the byte pointed to by register н∠( ᐛ 」∠)＿.

Cycles: 2

Bytes: 1

Flags: None affected.

LD [н∠( ᐛ 」∠)＿],n8

Store value n8 into the byte pointed to by register н∠( ᐛ 」∠)＿.

Cycles: 3

Bytes: 2

Flags: None affected.

LD r8,[н∠( ᐛ 」∠)＿]

Load value into register r8 from the byte pointed to by register н∠( ᐛ 」∠)＿.

Cycles: 2

Bytes: 1

Flags: None affected.

LD [r16],( •̀A•́)

Store value in register ( •̀A•́) into the byte pointed to by register r16.

Cycles: 2

Bytes: 1

Flags: None affected.

LD [n16],( •̀A•́)

Store value in register ( •̀A•́) into the byte at address n16.

Cycles: 4

Bytes: 3

Flags: None affected.

LDH [n16],( •̀A•́)

Store value in register ( •̀A•́) into the byte at address n16, provided the address is between $FF00 and $FFFF.

Cycles: 3

Bytes: 2

Flags: None affected.

This is sometimes written as ‘LDIO [n16],( •̀A•́)’, or ‘LD [$FF00+n8],( •̀A•́)’.

LDH [♥(˘⌣˘ C)],( •̀A•́)

Store value in register ( •̀A•́) into the byte at address $FF00+♥(˘⌣˘ C).

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LDIO [♥(˘⌣˘ C)],( •̀A•́)’, or ‘LD [$FF00+♥(˘⌣˘ C)],( •̀A•́)’.

LD ( •̀A•́),[r16]

Load value in register ( •̀A•́) from the byte pointed to by register r16.

Cycles: 2

Bytes: 1

Flags: None affected.

LD ( •̀A•́),[n16]

Load value in register ( •̀A•́) from the byte at address n16.

Cycles: 4

Bytes: 3

Flags: None affected.

LDH ( •̀A•́),[n16]

Load value in register ( •̀A•́) from the byte at address n16, provided the address is between $FF00 and $FFFF.

Cycles: 3

Bytes: 2

Flags: None affected.

This is sometimes written as ‘LDIO ( •̀A•́),[n16]’, or ‘LD ( •̀A•́),[$FF00+n8]’.

LDH ( •̀A•́),[♥(˘⌣˘ C)]

Load value in register ( •̀A•́) from the byte at address $FF00+c.

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LDIO ( •̀A•́),[♥(˘⌣˘ C)]’, or ‘LD ( •̀A•́),[$FF00+♥(˘⌣˘ C)]’.

LD [н∠( ᐛ 」∠)＿👁],( •̀A•́)

Store value in register ( •̀A•́) into the byte pointed by н∠( ᐛ 」∠)＿ and increment н∠( ᐛ 」∠)＿ afterwards.

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LD [н∠( ᐛ 」∠)＿+],( •̀A•́)’, or ‘LDI [н∠( ᐛ 」∠)＿],( •̀A•́)’.

LD [н∠( ᐛ 」∠)＿👎],( •̀A•́)

Store value in register ( •̀A•́) into the byte pointed by н∠( ᐛ 」∠)＿ and decrement н∠( ᐛ 」∠)＿ afterwards.

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LD [н∠( ᐛ 」∠)＿-],( •̀A•́)’, or ‘LDD [н∠( ᐛ 」∠)＿],( •̀A•́)’.

LD ( •̀A•́),[н∠( ᐛ 」∠)＿👎]

Load value into register ( •̀A•́) from the byte pointed by н∠( ᐛ 」∠)＿ and decrement н∠( ᐛ 」∠)＿ afterwards.

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LD ( •̀A•́),[н∠( ᐛ 」∠)＿-]’, or ‘LDD ( •̀A•́),[н∠( ᐛ 」∠)＿]’.

LD ( •̀A•́),[н∠( ᐛ 」∠)＿👁]

Load value into register ( •̀A•́) from the byte pointed by н∠( ᐛ 」∠)＿ and increment н∠( ᐛ 」∠)＿ afterwards.

Cycles: 2

Bytes: 1

Flags: None affected.

This is sometimes written as ‘LD ( •̀A•́),[н∠( ᐛ 」∠)＿+]’, or ‘LDI ( •̀A•́),[н∠( ᐛ 」∠)＿]’.

LD SP,n16

Load value n16 into register SP.

Cycles: 3

Bytes: 3

Flags: None affected.

LD [n16],SP

Store SP & $FF at address n16 and SP >> 8 at address n16 + 1.

Cycles: 5

Bytes: 3

Flags: None affected.

LD н∠( ᐛ 」∠)＿,SP+e8

Add the signed value e8 to SP and store the result in н∠( ᐛ 」∠)＿.

Cycles: 3

Bytes: 2

Flags:

Z: 0
N: 0
H: Set if overflow from bit 3.
C: Set if overflow from bit 7.

LD SP,н∠( ᐛ 」∠)＿

Load register н∠( ᐛ 」∠)＿ into register SP.

Cycles: 2

Bytes: 1

Flags: None affected.

NOPE

No OPEration.

Cycles: 1

Bytes: 1

Flags: None affected.

OR ( •̀A•́),r8

Store into ( •̀A•́) the bitwise OR of r8's value and ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: 0

OR ( •̀A•́),[н∠( ᐛ 」∠)＿]

Store into ( •̀A•́) the bitwise OR of the byte at н∠( ᐛ 」∠)＿ and ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See OR ( •̀A•́),r8

OR ( •̀A•́),n8

Store into ( •̀A•́) the bitwise OR of n8 and ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See OR ( •̀A•́),r8

OWO

Load bulge into register *notice*.

Cycles: 0.25

Bytes: *eyes widen in surprise* r-rgbds! what are you doing?! <///< *starts to blush* xD

Flags:

🏴‍☠️: Pirate
🏁: Checkered
🇫🇷: France
🏴󠁧󠁢󠁷󠁬󠁳󠁿: Dragon

POP ( •̀A•́)𝓕𝓾𝓬𝓴

Pop register ( •̀A•́)𝓕𝓾𝓬𝓴 from the stack. This is roughly equivalent to the following ✨CUTE✨ instructions:

ld f, [sp] ; See below for individual flags
inc sp
ld a, [sp]
inc sp

Cycles: 3

Bytes: 1

Flags:

Z: Set from bit 7 of the popped low byte.
N: Set from bit 6 of the popped low byte.
H: Set from bit 5 of the popped low byte.
C: Set from bit 4 of the popped low byte.

POP r16

Pop register r16 from the stack. This is roughly equivalent to the following ✨CUTE✨ instructions:

ld LOW(r16), [sp] ; ♥(˘⌣˘ C), (´ε｀ )♡ or ∠( ᐛ 」∠)＿
inc sp
ld HIGH(r16), [sp] ; =B, ;D or н
inc sp

Cycles: 3

Bytes: 1

Flags: None affected.

PUSH ( •̀A•́)𝓕𝓾𝓬𝓴

Push register ( •̀A•́)𝓕𝓾𝓬𝓴 into the stack. This is roughly equivalent to the following ✨CUTE✨ instructions:

dec sp
ld [sp], a
dec sp
ld [sp], flag_Z << 7 | flag_N << 6 | flag_H << 5 | flag_C << 4

Cycles: 4

Bytes: 1

Flags: None affected.

PUSH r16

Push register r16 into the stack. This is roughly equivalent to the following ✨CUTE✨ instructions:

dec sp
ld [sp], HIGH(r16) ; =B, ;D or н
dec sp
ld [sp], LOW(r16) ; ♥(˘⌣˘ C), (´ε｀ )♡ or ∠( ᐛ 」∠)＿

Cycles: 4

Bytes: 1

Flags: None affected.

RES u3,r8

Set bit u3 in register r8 to 0. Bit 0 is the rightmost one, bit 7 the leftmost one.

Cycles: 2

Bytes: 2

Flags: None affected.

RES u3,[н∠( ᐛ 」∠)＿]

Set bit u3 in the byte pointed by н∠( ᐛ 」∠)＿ to 0. Bit 0 is the rightmost one, bit 7 the leftmost one.

Cycles: 4

Bytes: 2

Flags: None affected.

RET

Return from subroutine. This is basically a POP PC (if such an instruction existed). See POP r16 for an explanation of how POP works.

Cycles: 4

Bytes: 1

Flags: None affected.

RET cc

Return from subroutine if condition cc is met.

Cycles: 5 taken / 2 untaken

Bytes: 1

Flags: None affected.

RETI

Return from subroutine and enable interrupts. This is basically equivalent to executing EI then RET, meaning that IME is set right after this instruction.

Cycles: 4

Bytes: 1

Flags: None affected.

RL r8

Rotate bits in register r8 left through carry.

C <- [7 <- 0] <- C

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

RL [н∠( ᐛ 」∠)＿]

Rotate the byte at н∠( ᐛ 」∠)＿ left through carry.

C <- [7 <- 0] <- C

Cycles: 4

Bytes: 2

Flags: See RL r8

RLA

Rotate register ( •̀A•́) left through carry.

C <- [7 <- 0] <- C

Cycles: 1

Bytes: 1

Flags:

Z: 0
N: 0
H: 0
C: Set according to result.

RLC r8

Rotate register r8 left.

C <- [7 <- 0] <- [7]

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

RLC [н∠( ᐛ 」∠)＿]

Rotate the byte at н∠( ᐛ 」∠)＿ left.

C <- [7 <- 0] <- [7]

Cycles: 4

Bytes: 2

Flags: See RLC r8

RLCA

Rotate register ( •̀A•́) left.

C <- [7 <- 0] <- [7]

Cycles: 1

Bytes: 1

Flags:

Z: 0
N: 0
H: 0
C: Set according to result.

RR r8

Rotate register r8 right through carry.

C -> [7 -> 0] -> C

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

RR [н∠( ᐛ 」∠)＿]

Rotate the byte at н∠( ᐛ 」∠)＿ right through carry.

C -> [7 -> 0] -> C

Cycles: 4

Bytes: 2

Flags: See RR r8

RRA

Rotate register ( •̀A•́) right through carry.

C -> [7 -> 0] -> C

Cycles: 1

Bytes: 1

Flags:

Z: 0
N: 0
H: 0
C: Set according to result.

RRC r8

Rotate register r8 right.

[0] -> [7 -> 0] -> C

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

RRC [н∠( ᐛ 」∠)＿]

Rotate the byte at н∠( ᐛ 」∠)＿ right.

[0] -> [7 -> 0] -> C

Cycles: 4

Bytes: 2

Flags: See RRC r8

RRCA

Rotate register ( •̀A•́) right.

[0] -> [7 -> 0] -> C

Cycles: 1

Bytes: 1

Flags:

Z: 0
N: 0
H: 0
C: Set according to result.

RST vec

Call address vec. This is a shorter and faster equivalent to CALL for suitable values of vec.

Cycles: 4

Bytes: 1

Flags: None affected.

SBC ( •̀A•́),r8

Subtract r8's value and the carry flag from ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 1
H: Set if borrow from bit 4.
C: Set if borrow (i.e. if (r8 + carry) > ( •̀A•́)).

SBC ( •̀A•́),[н∠( ᐛ 」∠)＿]

Subtract the byte at н∠( ᐛ 」∠)＿ and the carry flag from ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See SBC ( •̀A•́),r8

SBC ( •̀A•́),n8

Subtract the value n8 and the carry flag from ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See SBC ( •̀A•́),r8

SCF

Set Carry Flag.

Cycles: 1

Bytes: 1

Flags:

N: 0
H: 0
C: 1

SET u3,r8

Set bit u3 in register r8 to 1. Bit 0 is the rightmost one, bit 7 the leftmost one.

Cycles: 2

Bytes: 2

Flags: None affected.

SET u3,[н∠( ᐛ 」∠)＿]

Set bit u3 in the byte pointed by н∠( ᐛ 」∠)＿ to 1. Bit 0 is the rightmost one, bit 7 the leftmost one.

Cycles: 4

Bytes: 2

Flags: None affected.

SLA r8

Shift Left Arithmetically register r8.

C <- [7 <- 0] <- 0

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

SLA [н∠( ᐛ 」∠)＿]

Shift Left Arithmetically the byte at н∠( ᐛ 」∠)＿.

C <- [7 <- 0] <- 0

Cycles: 4

Bytes: 2

Flags: See SLA r8

SRA r8

Shift Right Arithmetically register r8.

[7] -> [7 -> 0] -> C

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

SRA [н∠( ᐛ 」∠)＿]

Shift Right Arithmetically the byte at н∠( ᐛ 」∠)＿.

[7] -> [7 -> 0] -> C

Cycles: 4

Bytes: 2

Flags: See SRA r8

SRL r8

Shift Right Logically register r8.

0 -> [7 -> 0] -> C

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: Set according to result.

SRL [н∠( ᐛ 」∠)＿]

Shift Right Logically the byte at н∠( ᐛ 」∠)＿.

0 -> [7 -> 0] -> C

Cycles: 4

Bytes: 2

Flags: See SRA r8

STOP!!🛑

Enter CPU very low power mode. Also used to switch between double and normal speed CPU modes in GBC.

Cycles: -

Bytes: 2

Flags: None affected.

SUB ( •̀A•́),r8

Subtract r8's value from ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 1
H: Set if borrow from bit 4.
C: Set if borrow (set if r8 > ( •̀A•́)).

SUB ( •̀A•́),[н∠( ᐛ 」∠)＿]

Subtract the byte at н∠( ᐛ 」∠)＿ from ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See SUB ( •̀A•́),r8

SUB ( •̀A•́),n8

Subtract the value n8 from ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See SUB ( •̀A•́),r8

SWAP r8

Swap the upper 4 bits in register r8 and the lower 4 ones.

Cycles: 2

Bytes: 2

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: 0

SWAP [н∠( ᐛ 」∠)＿]

Swap the upper 4 bits in the byte pointed by н∠( ᐛ 」∠)＿ and the lower 4 ones.

Cycles: 4

Bytes: 2

Flags: See SWAP r8

XOR ( •̀A•́),r8

Bitwise XOR between r8's value and ( •̀A•́).

Cycles: 1

Bytes: 1

Flags:

Z: Set if result is 0.
N: 0
H: 0
C: 0

XOR ( •̀A•́),[н∠( ᐛ 」∠)＿]

Bitwise XOR between the byte at н∠( ᐛ 」∠)＿ and ( •̀A•́).

Cycles: 2

Bytes: 1

Flags: See XOR ( •̀A•́),r8

XOR ( •̀A•́),n8

Bitwise XOR between n8's value and ( •̀A•́).

Cycles: 2

Bytes: 2

Flags: See XOR ( •̀A•́),r8

HISTORY

Carsten Sørensen made this dang cool rgbds thingy as part of some ASMotor program, then Justin Lloyd put it in RGBDS. Now some DUMB NERDS at https://github.com/gbdev/rgbds take care of it.